1. Field of the Invention
The present invention relates to wiring technologies for MOS LSIs and other semiconductor integrated circuits. The present invention more specifically relates to technologies of improving the integration density by changing the routing pitch of metal wiring layers to be connected to the sources and/or drains of MOS FETs that constitute basic cells in the customization of application specific integrated circuits (ASICs) and other semi-custom ICs.
2. Description of the Prior Art
While the full-custom IC fabrication methodology is suited to the mass-production of high-performance ICs, the semi-custom IC fabrication methodology represented by that of ASICs is suited to the speedy development of user-specific LSIs by computer-based automatic design based on logical cells prepared so as to comprise the functions of each level of SSIs, MSIs, and LSIs. Although full-custom design methodology employs computer-based automatic design, it applies automation mainly to the forecasting of circuit behavior and the verification of patterns. Moreover, it has standards in automatic design in the other fields, so that the designer must interact with the computer in designing of ICs.
The semi-custom design methodology, on the other hand, may be said to be provided with automatic design standards by use of computers. Gate arrays used in designing of an ASIC feature that identical basic cells such as shown in FIGS. 1A and 1B are partitioned and placed on a grid-shaped master chips 81 and 82 such as shown in FIGS. 2A and 2B, respectively. Then, the designer only has to customize the final contacts and metal wiring layers to be formed above the basic cells and conduct only wiring connection of those metal wiring layers as shown in FIGS. 3A and 3B, to complete a user-specific LSI.
The reasons why gate arrays can be developed in a short period of time are:
a) The fabrication processes are conducted only to last few steps of metal wiring layers; PA1 b) Time is rather short that is required for (preparation of) packaging and evaluation because the chip size and the number of pads are known beforehand; and PA1 c) Verification of functions does not take a long time with lesser mistakes and troubles because logics can be easily verified on the basis of pre-verified cells and automatic design (AD) of a target LSI.
FIG. 2A shows an example of gate-array chip configuration. In FIG. 2A, basic cells 61 are disposed in a row on a chip 81, between which are arranged horizontal wiring channel regions 63. In another example shown in FIG. 2B, basic cells are arranged in islands, between which wiring horizontal channel regions 65 and vertical wiring channel regions 66 are disposed. Both how to arrange the basic cells 61 and how to set the horizontal wiring channel regions 63 and 65 and vertical wiring channel regions 66 depend on the process technologies used, the construction of the basic cells 61, and the easiness of creating automatic arrangement/wiring programs. Each of the chips 81 and 82 has I/O cells on its periphery, each terminal of which comprises input buffers, output buffers, and bilateral buffers, depending on the wiring mask. The I/O cell 62 further has a bonding pad 71 on its periphery, which is connected to a package pin with a bonding wire made of gold etc.
By customizing metal wirings on such basic cells 61, each having a uniform mask pattern as shown in FIG. 1A or 1B, desired logical gates such as NOT, NAND, or NOR can be produced. Also, by customizing metal wiring on the wiring regions between those basic cells, the logical gates can be connected to each other. For example, as shown in FIGS. 3A and 3B, by routing metal wiring consisting of a lateral first level interconnection 6 (the deepest level metal wiring layers) and a second level interconnection 7 formed vertically via the overlying insulator film, a NAND circuit having two inputs can be configured.
Thus, for ASICs, by designing only a pattern of metal wiring layers consisting of such first level interconnection 6 and second level interconnection 7 as shown in FIGS. 3A and 3B above those basic cells 61 designed and registered beforehand, any connections can be produced. As a wiring channel region between cell rows, a first level interconnection 6 is used as a lateral (perpendicular to a gate polysilicon 1) metal wiring and an overlying second level interconnection 7, as a vertical (parallel to the gate polysilicon 1) metal wiring. As shown in FIG. 3B, however, part of the first level interconnection 6 parallel to the gate polysilicon is also designed. The lateral first level interconnection 6 and the vertical second level interconnection 7 are not electrically connected because they are on different levels mutually and insulated from each other with an insulator film, although they may be overlapped in a plan view of mask pattern. To electrically connect n.sup.+ source/drain regions 12 and p.sup.+ source/drain regions 22 in the basic cell 61 to the first level interconnection 6, it is necessary to use contact windows (contact holes) 3 and 74 in an inter-layer insulator film.
In design of ASICs, it is usual to design and register beforehand as a cell library in the computer such patterns as n.sup.+ source/drain regions 12, p.sup.+ source/drain regions 22, and gate polysilicon 1 of basic cell 61 of logical gates such as NAND, NOR, and NOT of an gate array. Also, even a large logical block can be realized by using a plurality of basic cells. Flip-flops and other basic composite gates are also designed and register in the computer beforehand. Each of those utilizes a plurality of basic cells, so that it is called a macro cell.
In a gate array, circuits each of which has the same number of gates can share the same basic-cell layer below a metal wiring layer. After logical design of a logical circuit is finished, layout design only has to be conducted on a metal wiring layer, to realize a desired circuit. By prefabricating the basic-cell parts other than the metal wiring layer, which is the top part of the chip, it is possible to reduce the costs of integrated circuits. In this sense, such type of ICs are used widely as semi-custom ICs.
The metal wiring usually is designed along a grid 90 such as shown in FIG. 1B. Each of the grids 90 has a prescribed pitch. And each of its intersections is prepared so that a square-shaped contact hole can be disposed according to a specification. FIG. 1B shows a basic cell that has two p.sup.+ regions 22 inside an n-well 9 and another two n.sup.+ regions 12 on a p-type substrate outside the n-well 9. Each of those n.sup.+ regions 12 and p.sup.+ regions 22 has therein two gate polysilicon 1 even spaced. In FIG. 1B, although intersection of the grid 90 and the gate polysilicon 1 are not overlapped, in an actual pattern, the gate polysilicon 1 has also an intersection placed thereon, so that it has a contact hole opened at prescribed positions of its self. A gate array circuit comprises a horizontal and a vertical arrays of such basic cells as shown in FIG. 1B disposed on such chips 81 as shown in FIGS. 2A and 2B. Then, first and second level interconnections are arranged along the grids, thus enabling automatic design.
FIGS. 3A and 3B respectively show first level interconnection 6 and second level interconnection 7 for two-input NAND circuits and another two-input AND circuits designed by an ASIC methodology. In FIG. 3A, a thin line 6 represents the first level interconnections, a bold line 7 represents the second level interconnections, and a solid circle represents contact holes 3, 74 and via hole 77 which constitute a two-input NAND circuit. The via hole 77 contacts exclusively between the first and second level interconnections. FIG. 3B is a plan view more specifically illustrating a two-input AND circuit, which comprises first level interconnections, second level interconnections 7, contact holes 3, 74, and 76, and via holes 77. Between the first and the second level interconnections is formed an inter-layer insulator film to isolate them from each other, being connected with them through via holes at prescribed positions. The first level interconnection is connected to the gate polysilicon 1 via the contact holes 76 and to the n.sup.+ source/drain regions 12 via the contact holes 3 and also to the p.sup.+ source/drain regions via the contact holes 74. FIGS. 4A and 4B show part of a plane pattern of conventional ASIC-MOS LSIs. FIG. 5A is a cross sectional view cut along the I--I line of FIG. 4A, while FIG. 5B is a cross section view cut along II--II line of FIG. 4A. By the conventional technology, as shown in the cross sectional view of FIG. 5A, on a channel region between the source region 12 and the drain region 12 is placed the gate polysilicon 1 via a gate oxide film, thus constituting an MOS transistor. Apart from the edge of the gate polysilicon by "a prescribed distance a" determined by the design rules (i.e., a margin for mask alignment), a contact hole 3 is opened to electrically interconnect the first level interconnection 6 and the source/drain regions of the MOS transistor. Also, the width of the gate polysilicon 1, that of the contact hole 3, and the distance between these determine a pitch for the grid 90, which also depend on the geometrical configuration of MOS transistors shown in FIG. 1B. As shown in FIG. 5B also, apart from the edge of the source/drain regions 12 by "a distance c" as a mask-alignment margin, contact holes 3 are opened.
FIG. 6A shows a partial plan view of the semiconductor integrated circuit composed of conventional LDD-MOS FETs, while FIG. 6B shows a cross sectional view of the circuit cut along the III--III line of FIG. 6A. By the LDD-MOST FET structure, it is necessary to form, as shown in FIG. 6B, contact holes 3 having low ohmic contact resistance to deep high-impurity concentration n.sup.+ source/drain regions 12. And "the distance e" between a gate polysilicon 1 and contact holes 3 is wider than that of the normal MOS FET structure. In the fabrication of ASICs, several tens to several hundreds of types of master chips are prefabricated corresponding to the kinds of gates (the number of transistors used), so that appropriate master chips can be selected corresponding to the scale of a desired LSI. To realize desired functions on thus selected master chips, basic cells are (automatically) disposed in consideration of the connection relationship between the cells. Then, a task of automatic inter-cell routing is conducted over the grids 90 as shown in FIG. 1B. The wiring channel regions of gate arrays are fixed as shown in FIGS. 2A and 2B. The channel routing is executed between device rows of logical cells by use of a wiring tool. Next, those signals not wired yet undergo routing by use of for example a maze running router. Any gates, if wired yet, is wired on the basis of interactive processing with the designer. In this case, also, in contrast to manual routing by the conventional full-custom design method, a method by the present invention generally only has to conduct routing in the database of computer which stores inter-cell connection information and the design rules, giving no mistakes in connection or design rules. Moreover, interactive routing, even if needed, should preferably be conducted without changing the contents of the database about the position, pitch, geometry of the grids, contact holes, first wiring layer 6, and second wiring layer 7 in the basic cells.
Any large-scale circuit system will almost in all cases comprises memories, CPU cores, ALUs, A/D and D/A converters, displays, and various I/O circuits, etc. If one chip intends to have a large scale of circuits, those sub-systems must naturally be integrated in one chip. This leads to the necessity of the hybridization of memories and logics as well as that of analog circuits and digital circuits. The hybridization of memories and logics has a problem of harmony between the pitch of memory bit lines and word lines and that of logics. Moreover, even when the same type of circuits are to be integrated in the same chip, there occurs a case that a part of the circuits is required to increase locally in integration density. In such a case that the hybridization is necessary or a part of integration density have to be changed, a wiring layer pitch (pitch 2) different from that for the basic cells (pitch 1) stored in a cell library may be necessitated.
The details of these problems are discussed below with reference to FIGS. 4A and 4B.
(a) FIG. 4B shows a case where the position of a first level interconnection 6 of the metal wirings for an LSI pattern designed according to the user's desired specifications does not match a first pitch (pitch 1) of contact holes 3 of a basic cell registered in a cell library. As already explained, the first level interconnection is supposed to be, as shown in FIG. 1B, formed along grids 90 and the contact holes are disposed, at the intersections of the grids 90 in the gate array architecture. Then, in this case, the first level interconnection 6 arranged along a second pitch (pitch 2) cannot be connected to source/drain regions 12 unless the pitch 1 is widened to move the contact holes 3 to the next intersection of the grids. If the pitch 1 is widened to a pitch 2, a "mask alignment margin c" cannot be assured which is, as shown in the cross sectional view of FIG. 5B, a distance from the edge of the source/drain region 12 to the right end of the contact hole 3, or the contact hole 3 would get out of the source/drain region 12. In order not to cause the contact hole 3 to do so, the source/drain regions 12 must be widened, by changing the basic cell patterns, which require time consuming pre-stage fabrication steps such as ion implantation steps and lose the advantages of gate array design methodology. Further, thus widened source/drain regions 12 increase parasitic resistance (source resistance and/or drain resistance) which is determined by the resistivity in the source and the drain regions as well as junction capacitance associated with the increased area of the source/drain regions, thus deteriorating the high-speed, high-frequency performances and noise characteristics.
(b) To match the first pitch (pitch 1) with a wider second pitch (pitch 2) means that the pitch for basic cell's gate polysilicon 1 cannot be narrowed, which inhibits the increase of degree of integration density in semiconductor ICs.
(c) In the fabrication of ASICs, contact holes are produced by automatic design, wherein square or rectangular patterns having a prescribed area are arranged at the intersections of the grids as shown in FIG. 1B. In this case, however, if the number of contact holes (or the number of grid intersections) connecting the first level interconnection 6 and the source/drain regions 12 is fixed, the contact resistance cannot be decreased below a certain lower limit. This problem is significant in a large transistor having a wide width W of the source-drain regions (channel width W such as shown in FIG. 4A), in such large transistor the increase of diffusion resistance along the channel width direction will deteriorate seriously the high-frequency performances.